1. Field of the Invention
This invention relates to a method of forming electrical interconnections which reduce the resistance of electrical conductive vias of semiconductor devices.
2. Brief Description of the Prior Art
The geometry of semiconductor device components is continually being reduced in size. In order to conserve space on the chip so that the number of components that can be placed upon a chip of given area can be increased, it has been necessary, among other factors, to decrease the diameters of vias formed in the semiconductor device which are used, for example, to interconnect plural different levels of metallization on the chip. In the fabrication of these smaller semiconductor devices and due to the decrease in via geometry and decrease in contact area therein, the electrical resistance through the vias has increased sufficiently to become a major concern. The industry has therefore sought to reduce the electrical resistance through the vias.
One prior art method of filling the vias has generally been to provide an electrically conductive metal, generally tungsten, in the via with a layer of aluminum at both mouths of the via making electrical interconnection between the tungsten in the via and the levels of metallization which were being interconnected. The tungsten, which has relatively high resistivity, is generally separated from the underlying metal layer and the titanium-containing via sidewalls by a layer of titanium nitride. As the via cross-section area is scaled down, the resistance of the via continually increases if the same material, e.g., tungsten, is used to fill the vias. Therefore, another prior art method uses aluminum to fill the vias utilizing the lower resistivity of the aluminum to advantage. The techniques used for filling the vias with aluminum have included high temperature aluminum reflow, high pressure extrusion of aluminum and a combination of chemical vapor deposited (CVD) and physical vapor deposited (PVD) aluminum. All of these techniques require the use of titanium and titanium nitride liner layers in the vias. The titanium layer is present in the via so as to alloy the via bottom interface and minimize variability of the via resistance. The titanium nitride layer often is required in the via to separate the titanium liner from the aluminum deposited thereover to prevent intermetallic reaction. There are additional specific reasons to use the titanium nitride layers, depending upon the technique used to form the aluminum plugs in the vias.
The titanium layer is deposited using collimated sputtering to improve coverage of titanium at the base of the small vias. Either ionized metal PVD (IMP) or longthrow techniques are used to improve the titanium nitride liner coverage. In the case of aluminum deposition by CVD and PVD, for example, the titanium nitride layer is required for proper nucleation along the sidewalls of the via. In the case of extruded aluminum, a liner layer is required to ease the flow of aluminum into the via holes. High pressure extrusion of aluminum has, thus far, been carried out with a high step coverage titanium nitride liner layer deposited using a long-throw chamber. Combined CVD/PVD aluminum technique has also utilized high step coverage titanium nitride liner layers deposited using such techniques as IMP or CVD. Step coverage is defined at the thickness of the titanium nitride layer at the bottom of the via divided by the titanium nitride layer thickness over the field regions (the surface from which the via extends).
The above prior art schemes have three metallic interfaces in the path of the current flow, it having been determined as a part of the present invention that each interface adds materially to the the electrical resistance through the via.